1. Field of the Invention
This invention relates to a method of producing a semiconductor wafer in which a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer having a less defect and containing a uniform and high concentration of Ge can be formed on an insulating layer inside SOI wafer.
2. Description of the Related Art
In a silicon MOS device, the speeding-up and the low power consumption are established by conducting the scale down according to a scaling rule or the reduction of an operating voltage. However, in case of a region having a gate length of not more than 100 nm, the above establishment becomes difficult. For this end, an SOI substrate and an introduction of strained silicon are examined. Particularly, a substrate formed by introducing the strained silicon into the SOI substrate is considered as an ultimate substrate and studies thereof are going forward.
In order to put such a substrate into practical use, it is required to control a distance from a buried oxide film to a strained silicon layer as a channel layer as far as possible for the development of an effect of SOI substrate structure suppressing an influence of stray capacitance. For this end, it is most desirable to directly deposit a strained Si layer just able the buried oxide film of the SOI structure, but it is common to use a strain-relaxed SiGe layer as an intermediate layer under present circumstances. That is, in order to completely develop the superiority of the strained silicon SOI substrate, it is necessary that the aforementioned distance from the buried oxide film to the strained silicon layer as a channel layer is controlled as far as possible but also the SiGe layer as an intermediate layer is strain-relaxed.
As the first method of forming the strain-relaxed SiGe layer is mentioned a method based on a combination of SOI substrate and SiGe epitaxial technology. For example, JP-A-H07-169926 discloses a method wherein a SiGe layer is formed on the existing SOI substrate to cause strain relaxation and a Si layer is formed on the strain-relaxed SiGe layer to provide a strained Si. In this method, however, the SiGe layer of not less than few μm is interposed between the buried oxide film and the active layer as the channel layer for reducing defects, so that the superiority of the SOI substrate structure can not be developed sufficiently.
As the second method of forming the strain-relaxed SiGe layer, for example, JP-A-2000-243946 discloses a method wherein a silicon single crystal substrate is used instead of the expensive SOI substrate and an oxygen-containing silicon layer, SiGe layer and Si layer are formed on the silicon single crystal substrate as a single crystal layer inheriting lattice information of the substrate and then subjected to a thermal oxidation treatment. In this method, however, the strain in the SiGe layer can not be relaxed sufficiently and also the sufficient strain is not added to the strained Si in the active layer, so that the superiority of the strained Si can not be developed.
As the third method of forming the strain-relaxed SiGe layer, for example, JP-A-2003-31495 discloses a method wherein the SiGe layer id formed on the SOI substrate and partly melted by heating to diffuse Ge into the SOI layer and then the SiGe layer is solidified to conduct strain relaxation. In the substrate prepared by this method, however, the defect density becomes higher.
As the fourth method of forming the strain-relaxed SiGe layer, for example, JP-A-H09-321307 discloses a method wherein the SiGe layer is formed on a silicon substrate and thereafter an oxygen ion is injected into the SiGe layer by an oxygen ion injection-separation method (SIMOX) to form a buried insulating layer in the SiGe layer and then a strained silicon layer is formed. In this method, however, the buried insulating layer is formed in the SiGe layer, so that there is a problem that the pressure resistance of the buried insulating layer is easily deteriorated due to the residual Ge, which badly affects the characteristics of the semiconductor element.